1. Field of the Invention
The present invention relates to fixed/floating-point arithmetic processors in general and to a multi-precision fixed/floating-point arithmetic processor comprising a multiplexed, multiple register data path circuit in particular.
2. Description of Prior Art
Many numerical processing algorithms require the execution of a large variety of fixed and floating-point operations. In many applications the operations are intimately linked with inputs to currently executing operations being derived from data operands computed one or two instructions previously.
When single-chip arithmetic processors are designed for processing the above-described algorithms, there is a need to provide a mechanism to save past results without a transfer off-chip, and to re-use past results saved on-chip. There is hence a requirement for on-chip data feedback and storage of temporary results.
In addition to a requirement for on-chip temporary storage and data feedback, there is also a requirement for providing data not only for single and two operand instructions but also for three operand instructions. For example, in signal processing, many algorithms can be decomposed into multiply/accumulate type instructions (A.times.B)+C. In data processing, field extraction instructions concatenate two 64-bit fields A, B and extract a 64-bit field beginning at bit position C.
In addition to the desirability of on-chip temporary storage and data feedback and a processor with a capability to selectively execute single, double and triple operand instructions, the execution of numerical processing algorithms, as described above, frequently requires the use of numerical constants in fixed and floating-point formats. For example, certain signal processing algorithms require the scaling of data by a factor of 1/2 or 2. If the constants 1/2 or 2 were provided on-chip in fixed and floating-point formats, it would minimize the number of off-chip accesses required to implement the scaling operation in the several formats.
There are currently single-chip floating-point processors comprising on-chip feedback circuits which include temporary storage registers such as, for example, the circuit disclosed in copending patent application Ser. No. 657,563, filed Oct. 3, 1984, entitled A METHOD AND APPARATUS FOR SUMMING PRODUCTS OF PAIRS OF NUMBERS, U.S. Pat. No. 4,692,888, which is assigned to the assignee of the present application.
In the above-identified single-chip processor, there is provided an ALU, a plurality of temporary storage registers, multiple feedback paths for transferring data from the output of the ALU to the input ports of the ALU and an on-chip constant store. As in other known single-chip processors, however, the latter processor has the disadvantages that it is designed around a two port ALU rather than a three port ALU, requires two feedback paths to transfer data from the output of the ALU to the ALU input ports instead of a single feedback path and is not provided with an on-chip source of user selectable numerical constants in both fixed and several floating-point formats. These disadvantages combine to require undesirably large amounts of chip area for implementing a high-speed fixed/floating- point processor and multiple off-chip data accesses in the execution of many three operand instructions and multiple-step operations.
In another prior known single-chip arithmetic processor, there is provided a three port ALU, a plurality of temporary storage registers, a random access memory (RAM) and a single feedback path to the RAM and the registers.
While using a single feedback path, principal disadvantages of the latter processor are that the ALU is not capable of performing floating-point operations and there is no provision for selectively transferring data from more than one of the registers to any one of the ALU input ports.